Member of Technical Staff - Formal Verification

Job details

Work model

On-site

Salary

Not listed by source

Location

Palo Alto

Other jobs from this company

How this role compares at Architect Labs

Architect Labs has 12 live roles in MeritLog’s job list across 4 job types, and 8 of them are in other. 0 of those jobs list a pay range. That is 0%.

These counts use the job boards we track and were checked within the last five minutes. We compare only full pay ranges in the same currency and time period.

Job description

About Architect Labs Architect is a frontier AI lab for specialized computing systems. We partner with AI labs, clouds / neoclouds, quant firms, physical AI companies, fabless companies, IP providers, system companies and advanced fabs to tape-out custom hardware co-designed for their next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team has led research teams at nearly every frontier AI lab and led chip programs for some of the most complex SoCs in the world. What You'll Do As a Member of Technical Staff - Formal Verification Engineer at Architect Labs, you'll own formal verification of the AI-generated chip design artifacts, from early specifications through tape-out. You'll turn design intent into assertions, build formal environments, and work directly with designers to formally verify complex designs. - Develop and execute formal verification plans using AI for hardware blocks and subsystems. Identify critical properties, define the scope of verification, and establish clear criteria for closure. - Work with the AI researchers to build Spec to SVA flows including test plans, formal testbenches that capture functional requirements, interface protocols, and corner cases. Review assumptions against the specification and the environment the block will operate in. - Drive proofs to completion using abstraction, decomposition, invariants, and appropriate solver strategies. Diagnose inconclusive results and make difficult designs tractable without hiding the behavior you need to verify. - Debug counterexamples, isolate root causes, and work with RTL designers to resolve issues. Turn bugs into regression properties that catch the same failure in future revisions. - Assess verification completeness through coverage analysis, reachability checks, vacuity checks, and assumption reviews. Document what has been proven, what remains open, and where simulation or other methods are needed. - Build reusable verification components and automate formal regressions, result tracking, and failure triage. Work with our formal methods and ML teams to bring these checks into the AI-driven design flow. What We'd Like to See Qualifications & Skills: - Degree: BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - RTL and Assertions: Strong SystemVerilog and SVA skills. You can read complex RTL, understand the microarchitecture, and write properties that accurately capture its intended behavior. - Formal Tools: Hands-on experience with tools such as Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal. You can build verification environments, debug failed proofs, and improve proof convergence. - Proof Techniques: Practical understanding of model checking, induction, abstraction, and assume-guarantee reasoning. You know how constraints and modeling choices affect what a proof actually establishes. - Hardware Understanding: Comfortable reasoning about control logic, pipelines, arbitration, buffering, and interface protocols, including reset behavior, backpressure, and concurrent transactions. - Engineering Rigor: Strong scripting skills in Python, Tcl, or similar languages. You build repeatable workflows and keep verification results traceable to requirements and design revisions. - Ownership: Comfortable working from incomplete specifications, resolving ambiguity with designers, and making clear technical judgments under tape-out deadlines. Bonus: - Experience owning formal verification sign-off for blocks or subsystems in a shipped chip. - Experience verifying AI accelerators, processor cores, cache coherence, memory systems, or interconnects. - Background in simulation-based verification and UVM, with a practical understanding of how formal and simulation complement each other. - Experience building formal verification infrastructure used across multiple projects or teams. - Familiarity with AI-generated RTL or using verification results to guide automated design and repair. - Experience as an early technical hire at a semiconductor or EDA startup. What We Offer - Competitive salary and meaningful equity stake - Fast-paced startup with autonomy and visible impact - A foundational role at the intersection of formal verification, AI, and silicon

• Associate Account Partner - QualityOneveeva · Remote
• Engagement Manager - Life Sciences R&Dveeva · Remote
• Principal Business Consultant - Commercialveeva · Remote
• Account Partner - Development Cloud - Southern Europeveeva · Remote
• Senior Consultant - MedTech Regulatory Implementationveeva · Remote
• Post-Implementation Consultant - Master Data Management Platformveeva · Remote