RTL Design Engineer

Job details

Work model

Hybrid

Salary

Not listed by source

Location

Austin, TX; Palo Alto, CA

Job description

We’re hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.   About Us: Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from –40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense.   We’ve raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.   The salary range for this position is $120,000–$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location.   RTL Design at Mythic: At Mythic, our RTL design team is at the heart of transforming our custom dataflow architecture into working silicon. RTL engineers take ownership of microarchitecture and RTL implementation, designing high-performance, low-power logic that enables our breakthrough AI hardware. The team works closely with architecture, custom analog IP, compiler, verification, emulation, and post-silicon teams to ensure every component integrates seamlessly into the full system. Because modern AI workloads push the limits of performance, memory, and efficiency, our RTL engineers apply creativity and rigor to deliver designs that meet aggressive PPA (performance, power, area) goals while ensuring correctness. We welcome engineers at all levels who are excited to tackle challenging design problems and play a key role in building the next generation of AI compute hardware.

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