EngineeringHybrid

RTL Design Engineer

Mythic · Hybrid

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Last seen by MeritLog September 12, 2026Source: LeverSource version: lever-postings-v1

MeritLog read this listing from Mythic's Lever job board and last checked it on September 12, 2026.

Source: the employer's Lever job board. Open the original listing for current details.

Job details

Work model: Hybrid
Salary: $120,000 – $225,000 per year
Location: Austin, TX; Palo Alto, CA

Hiring context

How this role compares at Mythic

Mythic has 32 live roles in MeritLog’s catalog across 6 job families, and 24 of them are in engineering. 18 of those listings publish a pay range, a disclosure rate of 56%.

This role's posted range of $120,000 – $225,000 per year sits above 0% of the 16 other Mythic roles quoted over the same currency and period.

Mythic concentrates this hiring in:

Counted across the job boards MeritLog tracks, at the time this page was served. Pay comparisons use only listings that publish a complete range in the same currency and period.

What the role asks for

What you'd do

Design and implement RTL for Mythic's next-generation AI processor.
Develop and optimize high-performance, low-power components including datapaths, controllers, memory subsystems, and interconnects.
Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness.
Drive timing closure by working with synthesis and physical design teams.
Participate in design reviews and contribute to improving RTL coding practices and methodologies.

What they're asking for

Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.Education
3+ years of industry experience in RTL design, microarchitecture, and architecture development.Experience
Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies).Skill
Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.Skill
Familiarity with timing constraints, physical design considerations, and EDA flows.Skill
Hands-on experience with simulation, synthesis, linting, and static timing analysis tools.Skill
Strong problem-solving and communication skills with ability to work in cross-functional teams.Skill

Parsed by MeritLog from the employer’s own posting. The full description follows below.

Job description

We’re hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from –40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense. We’ve raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000–$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. RTL Design at Mythic: At Mythic, our RTL design team is at the heart of transforming our custom dataflow architecture into working silicon. RTL engineers take ownership of microarchitecture and RTL implementation, designing high-performance, low-power logic that enables our breakthrough AI hardware. The team works closely with architecture, custom analog IP, compiler, verification, emulation, and post-silicon teams to ensure every component integrates seamlessly into the full system. Because modern AI workloads push the limits of performance, memory, and efficiency, our RTL engineers apply creativity and rigor to deliver designs that meet aggressive PPA (performance, power, area) goals while ensuring correctness. We welcome engineers at all levels who are excited to tackle challenging design problems and play a key role in building the next generation of AI compute hardware. Responsibilities • Design and implement RTL for Mythic's next-generation AI processor. • Develop and optimize high-performance, low-power components including datapaths, controllers, memory subsystems, and interconnects. • Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness. • Drive timing closure by working with synthesis and physical design teams. • Participate in design reviews and contribute to improving RTL coding practices and methodologies. Requirements • Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science. • 3+ years of industry experience in RTL design, microarchitecture, and architecture development. • Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies). • Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines. • Familiarity with timing constraints, physical design considerations, and EDA flows. • Hands-on experience with simulation, synthesis, linting, and static timing analysis tools. • Strong problem-solving and communication skills with ability to work in cross-functional teams. At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.

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