Senior Design Verification Engineer
Mythic · Hybrid
This listing is no longer verified as available.
MeritLog keeps this source-backed description for reference. Availability is not verified, and there is no application link here.
Source: the employer's Lever job board. Open the original listing for current details. Availability is not verified for this retained page.
Job details
- Work model
- Hybrid
- Salary
- Not listed by source
- Location
- Austin, TX; Palo Alto, CA
Job description
We’re hiring experienced Design Verification Engineers to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. About Us: Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from –40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense. We’ve raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000–$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. Design Verification at Mythic: At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the full system operates as intended. Because today’s AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.