Back to search
EngineeringOn-site

Sr DFT Engineer

Mythic · On-site

Apply
Last seen by MeritLog September 9, 2026Source: LeverSource version: lever-postings-v1

MeritLog read this listing from Mythic's Lever job board and last checked it on September 9, 2026.

Source: the employer's Lever job board. Open the original listing for current details.

Job details

Work model
On-site
Salary
Not listed by source
Location
Bangalore

Hiring context

How this role compares at Mythic

Mythic has 32 live roles in MeritLog’s catalog across 6 job families, and 25 of them are in engineering. 18 of those listings publish a pay range, a disclosure rate of 56%.

Mythic concentrates this hiring in:

Counted across the job boards MeritLog tracks, at the time this page was served. Pay comparisons use only listings that publish a complete range in the same currency and period.

Job description

About us: Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. Mythic's unique technology makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over USD 125M in a recent funding round and has offices in Palo Alto (CA, USA), Austin (TX, USA), and Bangalore (Karnataka, India). About This Role: Mythic is a fast-paced startup looking for individuals that enjoy wide-reaching and flexible roles. The primary responsibility for this position is implementaiton of DFT features on Mythic's chips.  You will be the working on all aspects of DFT for sub-system-level blocks which form the SoC. You will need to contribute, and ideally, have ownership of all the aspects of DFT such as MBIST, IJTAG, Scan and ATPG . You will contribute to the methodology development to establish flow for all DFT features and enable first-pass success of these chips. You are expected to be involved and contribute to every phase of the design cycle from Concept to Silicon. Beyond DFT for our novel chip architecture, this role also presents a unique opportunity to get involved with and learn more about state-of-the-art deep neural networks (DNNs). You will also be collaborating with the RTL design , Physical design, STA and analog design teams at Mythic.

Privacy choices

Analytics and advertising stay off unless you allow them. Private data stays out.

Read the privacy notice