ASIC Package SI/PI Engineer

Job details

Work model

Hybrid

Salary

$266K - $445K

Location

San Francisco

Hiring context

How this role compares at OpenAI

OpenAI has 793 live roles in MeritLog’s catalog across 14 job families, and 306 of them are in engineering. 661 of those listings publish a pay range, a disclosure rate of 83%.

This role's posted range of $266K - $445K sits above 68% of the 648 other OpenAI roles quoted over the same currency and period.

Counted across the job boards MeritLog tracks, at the time this page was served. Pay comparisons use only listings that publish a complete range in the same currency and period.

What the role asks for

Parsed by MeritLog from the employer’s own posting. The full description follows below.

Job description

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will - Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. - Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. - Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. - Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI requirements. - Develop channel loss, crosstalk, impedance, skew, return-loss, and link-budget requirements, and translate them into actionable package layout guidelines. - Perform package-level PDN analysis, including impedance, loop inductance, DCIR, EM, dynamic voltage droop, current distribution, decoupling optimization, and power/ground architecture. - Drive die/package co-design, including bump/BGA assignment, stack-up optimization, power/ground allocation, high-speed I/O placement, and package routing architecture. - Develop simulation methodologies and automation flows for early architecture exploration, design-space optimization, and repeatable SI/PI sign-off. Required Qualifications - 5+ years of experience in signal integrity, power integrity, high-speed interconnect design, PDN design and package electrical design. - Strong understanding of signal-integrity and power-integrity fundamentals, including transmission-line behavior, impedance, loss, crosstalk, return paths, power-distribution networks, inductance, decoupling, voltage droop, and current distribution. - Hands-on experience with electromagnetic and SI/PI simulation tools such as Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI/PowerDC, or equivalent. - Experience with package layout environments such as Cadence APD/SIP, including the ability to review and modify package structures for SI/PI optimization. - Experience developing automated design optimization flows for model extraction, simulation setup, post-processing, design-space exploration, or layout optimization. - Strong communication skills and the ability to work effectively across ASIC, package, PCB, system, mechanical, thermal, power, validation, and manufacturing teams. Preferred Qualifications - Hands-on experience with advanced 2.5D/3D packaging, silicon or organic interposers, bridge technologies, HBM integration, IVR integration, or large-body AI/HPC packages. - Experience developing early-stage SI/PI feasibility methodologies that support chip and package architecture decisions. - Experience with memory architecture and high-speed memory interfaces, including HBM and DDR/LPDDR. - Experience with high-speed laboratory validation using VNA, spectrum analyzers, TDR/TDT, high-bandwidth oscilloscopes, and probe-based measurements. - Knowledge of package and PCB material properties, including dielectric constant, loss tangent, copper roughness, and manufacturing variation. To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.  We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. For additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement https://cdn.openai.com/policies/eeo-policy-statement.pdf. Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations. To notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form https://form.asana.com/?d=57018692298241&k=5MqR40fZd7jlxVUh5J-UeA. No response will be provided to inquiries unrelated to job posting compliance. We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link https://form.asana.com/?k=bQ7w9h3iexRlicUdWRiwvg&d=57018692298241. OpenAI Global Applicant Privacy Policy https://cdn.openai.com/policies/global-employee-and-contractor-privacy-policy.pdf At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.