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Principal DFT Engineer

SambaNova · Not provided by source

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MeritLog keeps this source-backed description for reference. Availability is not verified, and there is no application link here.

Last seen by MeritLog September 12, 2026Source: GreenhouseSource version: greenhouse-job-board-v1

Source: the employer's Greenhouse job board. Open the original listing for current details. Availability is not verified for this retained page.

Job details

Work model
Not provided by source
Salary
Conflicting source ranges
Location
Austin, Texas, United States; San Jose, California, United States

What the role asks for

What you'd do

  • Define & implement block-level and SoC-level DFT architecture for large, hierarchical SoCs
  • Develop and maintain ATPG flows for stuck-at, at-speed and advanced fault models.
  • Develop scripts and automation for DFT insertion, ATPG, coverage analysis, pattern generation, and debug.
  • Develop and maintain JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure for internal test and debug access.
  • Generate production-quality ATPG and MBIST patterns and support deployment to ATE.
  • Work closely with STA and Physical Design teams on DFT timing closure
  • Support silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization.

What they're asking for

  • B.S. in computer science, computer engineering, or related fieldEducation
  • 10+ years relevant industry experienceExperience
  • Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG, and hierarchical DFTSkill
  • Hands-on experience with Siemens Tessent tool flow (preferred) or equivalent industry standard DFT toolsSkillPreferred
  • Familiarity with cell-aware ATPG, small-delay defects, IEEE 1500, IEEE 1687/IJTAG, and low-power DFT is highly desirableSkill
  • Strong understanding of advanced ATPG, silicon diagnosis, and failure localization methodologiesSkill
  • Experience with STA constraints & analysis for DFT modes & SDF simulationsSkill
  • Working knowledge of Verilog/System-Verilog simulators & waveform debuggingSkill
  • Experience with ATE pattern deployment and silicon bring-upSkillPreferred
  • Experience with multi-die/chiplet DFT, known-good-die test, or die-to-die interface testingSkillPreferred
  • Experience with large compute, AI accelerator, or HPC SoCsSkillPreferred

Parsed by MeritLog from the employer’s own posting. The full description follows below.

Job description

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) - a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value. About the role Sambanova is looking for a talented and motivated Principal Design for Test (DFT) Engineer to help us build state-of-the-art RDU chips for machine learning and artificial intelligence. We are looking for a highly hands-on engineer who will be responsible for DFT architecture and implementation, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips Responsibilities Your responsibilities will include: • Define & implement block-level and SoC-level DFT architecture for large, hierarchical SoCs • Develop and maintain ATPG flows for stuck-at, at-speed and advanced fault models. • Develop scripts and automation for DFT insertion, ATPG, coverage analysis, pattern generation, and debug. • Develop and maintain JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure for internal test and debug access. • Generate production-quality ATPG and MBIST patterns and support deployment to ATE. • Work closely with STA and Physical Design teams on DFT timing closure • Support silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization. Required Qualifications • B.S. in computer science, computer engineering, or related field • 10+ years relevant industry experience • Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG, and hierarchical DFT • Hands-on experience with Siemens Tessent tool flow (preferred) or equivalent industry standard DFT tools • Familiarity with cell-aware ATPG, small-delay defects, IEEE 1500, IEEE 1687/IJTAG, and low-power DFT is highly desirable • Strong understanding of advanced ATPG, silicon diagnosis, and failure localization methodologies • Experience with STA constraints & analysis for DFT modes & SDF simulations • Working knowledge of Verilog/System-Verilog simulators & waveform debugging Preferred Qualifications • Experience with ATE pattern deployment and silicon bring-up • Experience with multi-die/chiplet DFT, known-good-die test, or die-to-die interface testing • Experience with large compute, AI accelerator, or HPC SoCs Base Salary Range: Base Pay Range $180,000-$255,000 USD Submission Guidelines Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified. EEO Policy SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws. Benefits Summary for US-Based, Full-Time Employment Positions SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.

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