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EngineeringNot provided by source

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX · Not provided by source

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Last seen by MeritLog September 10, 2026Source: GreenhouseSource version: greenhouse-job-board-v1

MeritLog read this listing from SpaceX's Greenhouse job board and last checked it on September 10, 2026.

Source: the employer's Greenhouse job board. Open the original listing for current details.

Job details

Work model
Not provided by source
Salary
$165,000 – $260,000 per year
Location
Irvine, CA

Hiring context

How this role compares at SpaceX

SpaceX has 2,376 live roles in MeritLog’s catalog across 11 job families, and 1,425 of them are in engineering. 197 of those listings publish a pay range, a disclosure rate of 8%.

This role's posted range of $165,000 – $260,000 per year sits above 77% of the 195 other SpaceX roles quoted over the same currency and period.

Counted across the job boards MeritLog tracks, at the time this page was served. Pay comparisons use only listings that publish a complete range in the same currency and period.

What the role asks for

What you'd do

  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

What they're asking for

  • Bachelor’s degree in electrical engineering, computer engineering or computer scienceEducation
  • 5+ years of ASIC and/or physical design flow development experience in industryExperience
  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flowsSkillPreferred
  • Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithmsSkillPreferred
  • Knowledge of deep sub-micron FinFET and CMOS solid state physicsSkillPreferred
  • Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell librariesSkillPreferred
  • Understanding of CMOS power dissipation in deep submicron processes leakage/dynamicSkillPreferred
  • Familiar with CMOS analog circuit and physical designSkillPreferred
  • Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flowsSkillPreferred
  • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)SkillPreferred
  • Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environmentSkillPreferred
  • Ability to work extended hours and weekends as needed to meet critical project milestonesSkillPreferred

Parsed by MeritLog from the employer’s own posting. The full description follows below.

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks) • Develop/improve physical design methodologies and automation scripts for various implementation steps • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop BASIC QUALIFICATIONS: • Bachelor’s degree in electrical engineering, computer engineering or computer science • 5+ years of ASIC and/or physical design flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows • Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms • Knowledge of deep sub-micron FinFET and CMOS solid state physics • Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries • Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic • Familiar with CMOS analog circuit and physical design • Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.) • Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment ADDITIONAL REQUIREMENTS: • Ability to work extended hours and weekends as needed to meet critical project milestones COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year. ITAR REQUIREMENTS: • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here. SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

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